System-in-package (SiP) technology currently attempts to combine numerous different types of semiconductor devices within a single semiconductor package. Within these SiP packages, connections between semiconductor devices are often implemented using wire bonding to bond pads located in the periphery of the semiconductor devices. Flip-chip techniques having solder bumps have also been utilized; however, the solder bump grid for a particular semiconductor device is still connected to bond pad sites at the periphery of the semiconductor device. Further, SiP implementations are typically implemented as specific solutions for the particular semiconductor devices included within the SiP device.
FIG. 1 (Prior Art) is a block diagram of an embodiment 100 for an integrated circuit (IC) layout used for connecting a prior host processor device 102 to a prior secondary device 120. The integrated circuit represented for the host processor device 102 includes a plurality of different circuit block areas, which are represented by blocks 104, 106, 108, and 110. Further, regions 112 between these circuit blocks are typically used for additional drivers, logic circuitry, and/or routing circuitry related to the circuit blocks. In addition, peripheral regions are located at the edges of the integrated circuit for the host processor device 102. These peripheral regions are represented by the arrows between the edge of the integrated circuit and the circuit blocks 104, 106, 108, and 110. Typically, these peripheral regions or periphery for the host processor device 102 is used in part for bond pads that are in turn utilized for external connections. As depicted, four bond pads 118 within the periphery are shown that are used for making external connections to the secondary device 120.
The integrated circuit represented for the secondary device 120 also includes a plurality of different circuit block areas, which are represented by blocks 122 and 124. Further, region 126 is also located between these circuit blocks and can be used for additional drivers, logic circuitry, and/or routing circuitry related to the circuit blocks. The periphery for the integrated circuit for the secondary device 120, which is represented by the arrows between the edge of the integrated circuit and the circuit blocks 122 and 124, include four bond pads 128 that are used for making external connections to the host processor device 102. Once connected, the two devices 102 and 120 can be packaged together to form a single SiP device. While the bond pad connections provide connectivity, they also require driver circuitry to drive the external interfaces for the bond pad connections, and connection speeds are limited by the nature of the external connections.
Copper pillar (CuP) interconnect technology has been used in the past for dedicated connections to a particular secondary IC. This CuP interconnect technology relies upon copper pillar structures built on top of integrated circuits to provide CuP connections. The CuP connections allow for direct circuit connections to underlying circuitry. A prior memory solution has utilized CuP connections to stack multiple memory integrated circuits (ICs) on top of each other in a single memory SiP device. As such, the CuP connections were configured specifically to work with memory ICs. Another prior product development aid has used CuP connections to connect a microcontroller to a buddy development IC, which was used to collect operational data for the microcontroller during prototype development and was then removed. As such, the CuP connections were configured specifically to work with the buddy development IC and were effectively removed from use after production launch of the microcontroller when the buddy IC was no longer included in packaging.
Prior host processor IC devices have also used interconnect fabric circuitry for internal communications. FIG. 4 (Prior Art) is a block diagram of an embodiment 400 for a prior interconnect fabric (ICF) 405. As depicted, the ICF 405 includes input stages, decode blocks, and multiplexers. For the embodiment 400 depicted, input stage 420 is connected to a CPU (central processing unit) master block 404, a decode block 426, and multiplexers (MUXs) 432 and 434. Input stage 422 is connected to a DMA (direct memory access) master block 406, a decode block 428, and multiplexers (MUXs) 432 and 434. MUX 432 is also connected to a first slave block (SLAVE 1) 408, and MUX 434 is also connected to a second slave block (SLAVE 2) 410. During operation, communications from the master blocks 404 and 406 are routed to slave blocks 408 and 410 by decoding the destination device addresses within communication packages using decode blocks 426 and 428. Example slave blocks include memory and peripheral blocks that are integrated within the same integrated circuit as the master blocks 404 and 406 and the interconnect fabric (ICF) 405.